`timescale 1ns/1ns module fsm1( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// reg [2:0] current_state , next_state; parameter S0=3'd0, S1=3'd1, S2=3'd2, S3=3'd3; always@(posedge clk or negedge rst)begin if(!rst) current_state <= S0; else c...
