题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
reg [7:0] atemp;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        atemp <= 8'b0;
        match <= 1'b0;
    end
    else begin
        atemp <= {atemp[6:0],a};
    end
end
always @(posedge clk or negedge rst_n) begin
    if (atemp == 8'b01110001) begin
        match <= 1'b1;
    end
    else begin
        match <= 1'b0;
    end
end

endmodule