题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg data1;
always @(posedge clk or negedge rst)begin
    if(!rst)
        data1 <= 0;
    else if(!data)
        data1 <= data1;
    else
        data1 <= !data1;
end
always @(posedge clk or negedge rst)begin
    if(!rst)
        q <= 0;
    else if(!data1)
        q <= q;
    else
        q <= !q;
end

//*************code***********//
endmodule
/*
最近在学，下面我写的测试，可以交流一下。自测运行会超时，但是提交就成功

`timescale 1ns/1ns



module testbench();
  reg data;
	reg clk;
  reg rst;
  wire q;
  Tff_2 T_inst(
  .data(data), 
  .clk(clk), 
  .rst(rst),
  .q(q)  
);
  initial clk = 0;
	always #5 clk = ~clk;  // Create clock with period=10
// A testbench
  initial begin
    rst = 0;
    data = 0;
    #10;
    rst = 1;
    #50;
    data = 1;
    #50;
    data = 0;
    #50;
    data = 1;
    #50;
    $stop;
  end   
    
    
    
    
//end    
  initial begin
    $dumpfile("out.vcd");
    // This will dump all signal, which may not be useful
    //$dumpvars;
    // dumping only this module
    //$dumpvars(1, testbench);
    // dumping only these variable
    // the first number (level) is actually useless
    $dumpvars(0, testbench);
end  
    
endmodule
*/