题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
reg [3:0]state,next_state;
parameter s0 = 0;
parameter s1 = 1;
parameter s2 = 2;
parameter s3 = 3;
parameter s4 = 4;
parameter s5 = 5;
parameter s6 = 6;
parameter m1 = 7;
parameter m2 = 8;
parameter m3 = 9;
parameter m4 = 10;
parameter m5 = 11;
parameter m6 = 12;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		match <= 0;
		not_match <= 0;
		state<=0;
		next_state<=0;
	end
	else begin
		state <= next_state;
		match <= (next_state == s6);
		not_match <= (next_state == m6);
	end
end

always@(*)begin
	next_state = state;
	case(state)
	s0: next_state = data ? m1 : s1;
	s1: next_state = data ? s2 : m2;
	s2: next_state = data ? s3 : m3;
	s3: next_state = data ? s4 : m4;
	s4: next_state = data ? m5 : s5;
    s5: next_state = data ? m6 : s6;
	s6: next_state = data ? m1 : s1;
	m1: next_state = data ? m2 : m2;
	m2: next_state = data ? m3 : m3;
	m3: next_state = data ? m4 : m4;
	m4: next_state = data ? m5 : m5;
	m5: next_state = data ? m6 : m6;
	m6: next_state = data ? m1 : s1;
	default: next_state = s0;
	endcase
end
endmodule