题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
 localparam IDLE = 3'b000,
			S0 = 3'b001,
			S1 = 3'b010,
			S2 = 3'b011,
			S3 = 3'b100;

 reg [2:0] state,next_state;

 always @ (posedge clk or negedge rst_n) begin
	if (~rst_n)
	  state <= IDLE;
	else if (data_valid)
	  state <= next_state;
 end

 always @ (*) begin
	next_state = IDLE;
	case (state)
	IDLE: next_state = (data == 1'b0) ? S0 : IDLE;
	S0: next_state = (data == 1'b1) ? S1 : S0;
	S1: next_state = (data == 1'b1) ? S2 : S0;
	S2: next_state = (data == 1'b0) ? S3 : IDLE;
	S3: next_state = (data == 1'b0) ? S0 : IDLE;
	default: next_state = IDLE;
	endcase
 end

 always @ (posedge clk or negedge rst_n) begin
	if (~rst_n)
	  match <= 1'b0;
	else if ((next_state == S3) && data_valid)
	  match <= 1'b1;
	else
	  match <= 1'b0;
 end
  
endmodule