题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);

	reg q,q_reg1,q_reg2,q_reg3;
	//高电平检测

	always @(posedge clka or negedge rst_n)
		if(!rst_n)
			q <= 0;
		else if(sig_a)
			q <= ~q;
		else
			q <= q;
	
	//两级寄存器触发
	always@ (posedge clkb or negedge rst_n)
		if(!rst_n)begin
			q_reg1<=0;
			q_reg2<=0;
		end
		else begin
			q_reg1<=q;
			q_reg2<=q_reg1;
		end

	//边沿检测
	always@ (posedge clkb or negedge rst_n)
		if(!rst_n)
			q_reg3<=0;
		else
			q_reg3 <= q_reg2;
	
	wire sig_b;
	assign sig_b = q_reg2 ^q_reg3;

    
endmodule