`timescale 1ns/1ns //换成移位和加即可 module calculation( input clk, input rst_n, input [3:0] a, input [3:0] b, output [8:0] c ); //12 1100,5 0101 reg [8:0] c; reg [7:0] temp_a2, temp_a3, temp_b1, temp_b2; always @(posedge clk or negedge rst_n) if(!rst_n) begin temp_a2 <= 'd...