`timescale 1ns/1ns module det_moore( input clk , input rst_n , input din , output reg Y ); //五个状态 parameter [2:0] IDLE=3'd0, S1 =3'd1, S2 =3'd2, S3 =3'd3, S4 =3'd4; reg [2:0] state,next_state; always@(posedge clk or negedge rst_n) if(!rst_n) state <= IDLE; else state <= next_state; //状态转移 alwa...