题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

parameter	[2:0]	IDLE = 3'd0,
					GET_0 = 3'd1,
					GET_01 = 3'd2,
					GET_011 = 3'd3,
					GET_0110 = 3'd4;

reg		[2:0]	c_state,n_state;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		c_state <= IDLE;
	else
		c_state <= n_state;

always@(*)
	if(data_valid)
		case(c_state)
		IDLE		:	n_state = data ? IDLE	 	: GET_0		;
		GET_0		:	n_state = data ? GET_01 	: GET_0		;
		GET_01		:	n_state = data ? GET_011 	: GET_0		;
		GET_011		:	n_state = data ? IDLE	 	: GET_0110	;
		GET_0110	:	n_state = data ? GET_01		: GET_0		;
		endcase
	else
		n_state = n_state;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		match = 1'b0;
	else if(data_valid & n_state[2])	//这里给通过的答案和题目描述不一样，按题目描述应该用c_state
		match = 1'b1;
	else
		match = 1'b0;
endmodule