题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
reg [7:0]c_r1;
always@(posedge clk or negedge rst_n)
begin if(~rst_n)
		c_r1 <=8'h0;
		else 
		c_r1 <=c;
end


wire  [7:0]mid;
min min1(
.data_a(b),
.data_b(a),
.clk(clk),
.rst_n(rst_n),
.data_min(mid)
);

min min2(
.data_a(c_r1),
.data_b(mid),
.clk(clk),
.rst_n(rst_n),
.data_min(d)
);





endmodule

module min(
input wire [7:0] data_a,
input wire [7:0] data_b,
	input clk,
	input rst_n,
output reg [7:0] data_min
);
always@(posedge clk or negedge rst_n)
begin if(~rst_n)
		data_min <=8'h0;
		else 
		begin 
		 if(data_a > data_b)
		 data_min<=data_b;
		 else
		 data_min<=data_a;
		end
end
endmodule