题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

wire rst_n = rst;

//*************code***********//

	// 状态机比较好写
	localparam 
	s0 = 5'b00000,
	s1 = 5'b00001,
	s2 = 5'b00010,
	s3 = 5'b00100,
	s4 = 5'b01000,
	s5 = 5'b10000;

	reg [4:0] cur_st;
	reg [4:0] nxt_st;

	always @(posedge clk or negedge rst_n) 
	begin
		if(~rst_n)
			cur_st <= s0;
		else
			cur_st <= nxt_st;
	end

	always @( *) begin
		case (cur_st)
			s0: nxt_st = data? s1 : s0;
			s1: nxt_st = data? s1 : s2;
			s2: nxt_st = data? s3 : s0;
			s3: nxt_st = data? s4 : s2;
			s4: nxt_st = data? s5 : s2;
			s5: nxt_st = data? s1 : s0;
			default:
				nxt_st = s0;
		endcase
	end

	always @(posedge clk or negedge rst_n) 
	begin
		if(~rst_n)
			flag <= 1'b0;
		else begin
			flag <= (nxt_st==s5);
		end
	end

//*************code***********//
endmodule

状态机解题，Moore型状态机。

先画图再写代码。