题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
	reg [6:0] lfsr;
	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			lfsr <= 'b0;
		end
		else begin
			lfsr <= {lfsr[5:0],a};
		end
	end
	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			match <= 'b0;
		end
		else begin
			if(lfsr == 8'b01110001)	match <= 1'b1;
			else 					match <= 1'b0;
		end
	end

endmodule