题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
wire [3:0] dd0;
wire [3:0] dd1;
wire [3:0] dd2;
wire [3:0] dd3;
reg [15:0] d_dly;
reg        vld_dly;
reg [4:0] out_tmp;

assign dd0 = d_dly[3:0];
assign dd1 = d_dly[7:4];
assign dd2 = d_dly[11:8];
assign dd3 = d_dly[15:12];

always@(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
        d_dly <= 16'd0;
    end
    else begin
        if(sel == 2'd0) begin
            d_dly <= d;
        end
        else;
    end
end

always@(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
        vld_dly <= 1'b0;
    end
    else begin
        if(sel == 2'd0) begin
            vld_dly <= 1'b0;
        end
        else begin
            vld_dly <= 1'b1;
        end
    end
end

assign validout = vld_dly;
assign out = out_tmp;

always@(*) begin
    case(sel)
        2'd0: out_tmp = 5'd0;
        2'd1: out_tmp = dd0+dd1;
        2'd2: out_tmp = dd0+dd2;
        2'd3: out_tmp = dd0+dd3;
        default: out_tmp = 5'd0;
    endcase
end

//*************code***********//
endmodule