题解 | #五到一选择器#

`timescale 1ns/1ns

module top_module( 
    input [3:0] a, b, c, d, e, 
    input [2:0] sel,
    output reg [3:0] out );
        always@(*)begin
            case(sel)
             3'b000: out = a;
             3'b001: out = b;
             3'b010: out = c;
             3'b011: out = d;
             4'b100: out = e;
             default: out = 0;
            endcase
        end
        
endmodule