题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
	parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8;
	reg [3:0] state,state_next;

always @(*) begin

case(state)
S0:begin if(a)  state_next=S0; else state_next=S1; end
S1:begin  if(a)  state_next=S2; else state_next=S1; end
S2:begin  if(a)  state_next=S3; else state_next=S1; end
S3:begin  if(a)  state_next=S4; else state_next=S1; end
S4:begin  if(a)  state_next=S0; else state_next=S5; end
S5:begin  if(a)  state_next=S0; else state_next=S6; end
S6:begin  if(a)  state_next=S0; else state_next=S7; end
S7:begin  if(a) state_next=S8; else  state_next=S1;end
S8:begin  if(a) state_next=S0; else  state_next=S1;end
default:begin if(a) state_next=S0; else  state_next=S1;end
endcase
end
  
  always @(posedge clk or negedge rst_n) begin
if(rst_n==0)
state<=S0;
else state<=state_next;
  end
   always @(posedge clk or negedge rst_n) begin
if(rst_n==0)
match<=0;
else match<=(state==S8)?1:0;
  end
endmodule