题解 | #RAM的简单实现#
RAM的简单实现
https://www.nowcoder.com/practice/2c17c36120d0425289cfac0855c28796
`timescale 1ns/1ns module ram_mod( input clk, input rst_n, input write_en, input [7:0]write_addr, input [3:0]write_data, input read_en, input [7:0]read_addr, output reg [3:0]read_data ); integer i; reg [3:0]buff[7:0]; always@(posedge clk or negedge rst_n)begin if(!rst_n) begin for(i=0;i<8;i=i+1) buff[i]<=0; end else if(write_en) buff[write_addr]<=write_data; end always@(posedge clk or negedge rst_n)begin if(!rst_n) read_data<=0; if(read_en) read_data<=buff[read_addr]; end endmodule