题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output reg clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
reg[7:0]cnt;
reg[7:0]cnt_e;
reg[7:0]cnt_o;
always@(posedge clk_in or negedge rst)
begin if(!rst)
 cnt<=0;
else if(cnt==M_N-1)
   cnt<=0;
   else cnt<=cnt+1;
end
always@(posedge clk_in or negedge rst)
begin if(!rst)
   begin 
         cnt_e<=0;
         cnt_o<=0;
   end
else if(cnt<c89)
 if (cnt_e==div_e-1)
     begin  cnt_e<=0; cnt_o<=0;  end 
  else begin  cnt_e<=cnt_e+1; cnt_o<=0; end

else  if(cnt_o==div_o-1)
   begin cnt_o<=0;
cnt_e<=0; end 
  else begin 
    cnt_o<=cnt_o+1; cnt_e<=0; end
end

always@(posedge clk_in or negedge rst)
begin if(!rst)
    clk_out<=0;
    else if(cnt<=c89)
     begin if((cnt_e==0)|(cnt_e==4))
     clk_out<=~clk_out; end
     else if((cnt_o==0)|((cnt_o==4)))
    clk_out<=~clk_out;
     end

//*************code***********//
endmodule