题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
  reg data_valid_d;
  always@(posedge clk or negedge rst_n)
 begin if(!rst_n)
 data_valid_d<=0;
 else data_valid_d<=data_valid;
 end
  reg[3:0]buff;
 always@(posedge clk or negedge rst_n)
 begin if(!rst_n)
  buff<=0;
  else if(data_valid)
  buff<={buff[2:0],data};
  else buff<=buff;
 end
always@(*)
 begin if(!rst_n)
 match=0;
 else if((buff==4'b0110)&data_valid_d)
 match=1;
 else match=0;
 end 

endmodule