题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	reg[3:0]cnt;
    reg [3:0]cnt_reg;
	always@(posedge clk or negedge rst_n)
	begin if(!rst_n)
    cnt<=0;
	else if(cnt==5)
    cnt<=0;
	else cnt<=cnt+1;
	end  
always@(posedge clk or negedge rst_n)
	begin if(!rst_n)
	cnt_reg<=0;
	else 
	cnt_reg<=cnt;
	end  
	reg [5:0]buff;
	always@(posedge clk or negedge rst_n)
	begin if(!rst_n)
	buff<=0;
	else buff<={buff[4:0],data};
	end

	always@(*)
	begin if(!rst_n) 
	begin match=0; not_match=0; end
	else if(cnt_reg==5) begin
	if(buff==6'b011100)
	begin match=1; not_match=0; end
    else 
	begin match=0; not_match=1; end
	end
	else begin match=0; not_match=0; end
	end 
endmodule