题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

 reg[7:0]buff;
 always@(posedge clk or negedge rst_n)
 begin if(!rst_n)
    buff<=8'b0;
	else buff<={buff[6:0],a};
 end 

 always@(posedge clk or negedge rst_n)
 begin if(!rst_n)
    match<=0;
	else if(buff===8'b01110001)
	match<=1;
	else match<=0;
 end 
endmodule