题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
reg [1:0]state;
reg [1:0]next_state;

//1
always@(posedge clk or negedge rst)
begin  if(!rst)
   state<=0;
   else state<=next_state;
end

//2
always@(*)
begin case(state)
s0: if(data) next_state=s1; else next_state=s0;
s1: if(data) next_state=s2; else next_state=s1;
s2: if(data) next_state=s3; else next_state=s2;
s3: if(data) next_state=s0; else next_state=s3;
endcase
end 

//3
always@(posedge clk or negedge rst)
begin if(!rst)
  flag<=0;
  else if((next_state==s0)&(data==1))
  flag<=1;
  else  flag<=0;
  end

//*************code***********//
endmodule