题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    reg clk_out2,
    output    reg clk_out4,
    output    reg clk_out8
    );
//*************code***********//
reg [2:0]cnt2;
reg [2:0]cnt4;
reg [2:0]cnt8;
always@(posedge clk_in or negedge rst)
begin if(!rst)
   cnt8<=0;
   else if(cnt8==7)
  cnt8<=0;
  else cnt8<=cnt8+1;
end
always@(posedge clk_in or negedge rst)
begin if(!rst)
   clk_out8<=0;
   else if(cnt8<4)
   clk_out8<=1;
   else clk_out8<=0;
end
always@(posedge clk_in or negedge rst)
begin if(!rst)
   cnt4<=0;
   else if(cnt4==3)
  cnt4<=0;
  else cnt4<=cnt4+1;
end
always@(posedge clk_in or negedge rst)
begin if(!rst)
   clk_out4<=0;
   else if(cnt4<2)
   clk_out4<=1;
   else clk_out4<=0;
end
always@(posedge clk_in or negedge rst)
begin if(!rst)
   clk_out2<=0;
   else clk_out2<=~clk_out2;
end
//*************code***********//
endmodule