题解 | #序列发生器#

序列发生器

https://www.nowcoder.com/practice/1fe78a981bd640edb35b91d467341061

序列发生器多种解法：

解法1、二阶段moore状态机：

注意点：

1、就离谱，状态机都写不利索了。是把下一状态赋值给当前状态。state <= n_state;

2、还有个问题，就是多了一个idle状态，为什么必须要一个idle状态？本题加idle是因为牛客网题目的问题吗？这样第一次输出变成了0001001？

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

    parameter [2:0] s0 = 3'd0, s1 = 3'd1, s2 = 3'd2, s3 = 3'd3, s4 = 3'd4, s5 = 3'd5, idle = 3'd6;
    reg [2:0] state, n_state;
    always@(posedge clk, negedge rst_n) begin
        if(~rst_n) begin
            n_state <= s0;
        end
        else begin
            n_state <= state;
        end
    end
    
    always@(posedge clk, negedge rst_n) begin
        if(~rst_n) begin
            state <= idle;
        end
        else begin
            state <= n_state;
        end
    end
    
    always @ (*) begin
        case(state) 
            idle: begin
                n_state <= s0;
                data <= 1'b0;
            end
            
            s0: begin
                n_state <= s1;
                data <= 1'b0;
            end
            s1: begin
                n_state <= s2;
                data <= 1'b0;
            end
            s2: begin
                n_state <= s3;
                data <= 1'b1;
            end
            s3: begin
                n_state <= s4;
                data <= 1'b0;
            end
            s4: begin
                n_state <= s5;
                data <= 1'b1;
            end
            s5: begin
                n_state <= s0;
                data <= 1'b1;
            end
            default: begin
                n_state <= s0;
                data <= 1'b0;
            end      
        endcase
    end
    
endmodule

解法2：移位

一开始没想出来

注意点：

1、在复位时赋初值，等效初始化，提供了一个思路，有时候初始化可以用复位赋初值代替

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
    
 //方法2：移位
    reg [5:0] seque;
    always@(posedge clk, negedge rst_n) begin
        if(~rst_n) begin
            seque <= 6'b001011;
        end
        else begin
            seque <= {seque[4:0], seque[5]};
        end
    end   
    always@(posedge clk, negedge rst_n) begin
        if(~rst_n) begin
            data <= 1'b0;
        end
        else begin
            data <= seque[5];
        end
    end 

endmodule