题解 | #异步复位的串联T触发器#

Verilog Tips
纯组合always程序块中的语句强烈推荐只使用阻塞赋值符号，而时序always程序块中推荐只使用非阻塞赋值符号，否则会带来非常多的隐患。
Verilog Code

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg tmp;
    always @(posedge clk or negedge rst)
        begin
            if(~rst)
                begin
                    tmp<=0;
                end
            else if(data)
                begin
                    tmp<=~tmp;
                end
            else
                begin
                    tmp<=tmp;
                end
        end
    always @(posedge clk or negedge rst)
        begin
            if(~rst)
                begin
                    q<=0;
                end
            else if(tmp)
                begin
                    q<=~q;
                end
            else
                begin
                    q<=q;
                end
        end 
//*************code***********//
endmodule

Testbench Code

`timescale 1ns/1ns
module testbench();
	reg clk=0;
	always #5 clk = ~clk;  // Create clock with period=10
// A testbench
    reg data=0,rst=0;
    initial begin
        #10 rst = 1;
        #210 $finish;
    end
    always
        begin
            #60 data = ~data;
        end
//end    
    initial begin
        $dumpfile("out.vcd");
        $dumpvars(0, testbench);
    end  
    Tff_2 test(.data(data),
               .clk(clk),
               .rst(rst),
               .q(q));
endmodule