题解 | #不重叠序列检测#

最常规的思路 `timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); reg[3:0] state; reg flag; always @ (posedge clk or negedge rst_n)begin if(!rst_n)begin flag<=1'b0; state<=4'd0; match<=0; not_match<=0; end else case(state) 4'd0:begin match<=0; not_match<=0; state<=state+1'b1; if(data==0) begin flag<=1'b1;end else begin flag<=1'b0;end end 4'd1:begin state<=state+1'b1; if(flag==1'b1 && data==1) begin flag<=1'b1;end else begin flag<=1'b0;end end 4'd2:begin state<=state+1'b1; if(flag==1'b1 && data==1) begin flag<=1'b1;end else begin flag<=1'b0;end end 4'd3:begin state<=state+1'b1; if(flag==1'b1 && data==1) begin flag<=1'b1;end else begin flag<=1'b0; end end 4'd4:begin state<=state+1'b1; if(flag==1'b1 && data==0) begin flag<=1'b1;end else begin flag<=1'b0;end end 4'd5:begin state<=4'd0; if(flag==1'b1 && data==0) begin match<=1'b1;end else begin not_match<=1'b1;end end endcase end endmodule