题解 | 脉冲同步器（快到慢）

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);

//将clka脉冲信号转成电平信号
reg sig_a_dly;
always@(posedge clka or negedge rst_n)
begin
	if(!rst_n)
		sig_a_dly <= 1'b0;
	else if(sig_a)
	//注意这个
		sig_a_dly <= ~sig_a_dly;
	else 
		sig_a_dly <= sig_a_dly;
end

//在clkb时钟下去采样clka时钟下的电平信号
reg sig_b_vld;
always@(posedge clkb or negedge rst_n)
begin
	if(!rst_n)
		sig_b_vld <= 1'b0;
	else
		sig_b_vld <= sig_a_dly;

end

reg sig_b_vld_dly;
always@(posedge clkb or negedge rst_n)
begin
	if(!rst_n)
		sig_b_vld_dly <= 1'b0;
	else
		sig_b_vld_dly <= sig_b_vld;
end

reg sig_b_vld_dly1;
always@(posedge clkb or negedge rst_n)
begin
	if(!rst_n)
		sig_b_vld_dly1 <= 1'b0;
	else
		sig_b_vld_dly1 <= sig_b_vld_dly;
end

assign sig_b = sig_b_vld_dly ^ sig_b_vld_dly1;

endmodule