题解 | 状态机与时钟分频

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
reg [2:0] cnt4;
reg [2:0] cnt4_N;

always@(*)
begin
	if(cnt4 == 3'd3)
		cnt4_N = 3'd0;
	else
		cnt4_N = cnt4 +3'd1;
end 

always@(posedge clk or negedge rst)
begin
	if(!rst)
		cnt4 <= 3'd0;
	else
		cnt4 <= cnt4_N;
end

always@(*)
begin
	if(cnt4 == 3'd1)
		clk_out = 1'd1;
	else
		clk_out = 1'd0;		
end

//*************code***********//
endmodule