题解 | 使用子模块实现三输入数的大小比较

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
	wire [7:0] ab;
	wire [7:0] ac;
	compare AB(clk,rst_n,a,b,ab);
	compare AC(clk,rst_n,a,c,ac);
	compare min(clk,rst_n,ab,ac,d);
endmodule

module compare(
	input clk,
	input rst_n,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] c
);
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		c<=0;
		else if(a<b)
		c<=a;
		else
		c<=b;
	end
endmodule