题解 | 数据串转并电路

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0]cnt;


//计数器逻辑
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt     <= 3'b0;
	end
	else if(valid_a)begin
		if(cnt == 3'd5) cnt <= 3'd0;
		else cnt <= cnt+3'd1;
	end 
	else cnt <= cnt;//无效就保持计数不变
end

//ready_a有效逻辑
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		ready_a     <= 1'b0;
	end
	else ready_a     <= 1'b1;
end

//数据移位逻辑
reg [5:0]data_a_buf;//用来缓存输入的数据

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		ready_a <= 1'b0;
		valid_b <= 1'b0;
		data_b  <= 6'b0;
		data_a_buf <= 6'b0;
	end
	else if(valid_a && ready_a)begin
		if(cnt < 5) begin
			data_a_buf <= {data_a,data_a_buf[5:1]};
			valid_b <= 1'b0;
			end
		else if(cnt == 5)begin
			data_b <= {data_a,data_a_buf[5:1]};
			valid_b <= 1'b1;
		end
	end 
	else begin
			valid_b <= 1'b0;	
	end
end



endmodule