题解 | 位拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0]d_reg;//寄存输入的有效值
always @(posedge clk or negedge rst)begin
if(!rst)begin
    d_reg <= 16'd0;
    out <= 5'd0;
    validout <=0;
end
else begin
    case(sel)
    0:begin
d_reg <= d;
out <= 5'd0;
validout <=0;
    end
    1:begin
d_reg <= d_reg;
out <= d_reg[3:0] + d_reg[7:4];
validout <=1;
end
2:begin
d_reg <= d_reg;
out <= d_reg[3:0] + d_reg[11:8];
validout <=1;
end
3:begin
d_reg <= d_reg;
out <= d_reg[3:0] + d_reg[15:12];
validout <=1;
end
default:begin
    d_reg <= 16'd0;
    out <= 5'd0;
    validout <=0;
end
    endcase
end
end
//*************code***********//
endmodule

一定要注意题目所说： sel = 0:   不输出且只有此时的输入有效 ，因此需要把输入的寄存，故定义一个d_reg;

其次要注意：case（sel）之后要有endcase，就算我们已经sel用了所用情况，为了保持好习惯一定要default！！！！！