题解 | 使用8线-3线优先编码器Ⅰ实现16线-4线优先编码器

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule

module encoder_164(
   input      [15:0]      A   ,
   input                  EI  ,
   
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);

// A[15:8] A[7:0]

wire [2:0] L_h;
wire GS_h, EO_h;

wire [2:0] L_l;
wire GS_l, EO_l;

encoder_83 ecd83h(
    .I(A[15:8]),
    .EI(EI),
    .Y(L_h),
    .GS(GS_h),
    .EO(EO_h)
);

encoder_83 ecd83l(
    .I(A[7:0]),
    .EI(EO_h),
    .Y(L_l),
    .GS(GS_l),
    .EO(EO_l)
);

assign L = {GS_h, L_h | L_l};
assign GS = GS_h | GS_l;
assign EO = EO_h & EO_l;



endmodule