题解 | 流水线乘法器

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);

wire[2*size-1:0] 	mul_bits[size-1:0];
reg [2*size-1:0] 	mul_01;
reg [2*size-1:0] 	mul_23;

//2级流水线
genvar i;
generate
	for(i=0; i<size; i=i+1) begin:mul
		assign mul_bits[i] = (mul_b[i])? mul_a<<i : 'd0; 	//乘
	end
endgenerate

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		mul_01 <= 'd0;
		mul_23 <= 'd0;
		mul_out<= 'd0;
	end
	else begin
		mul_01 <= mul_bits[0] + mul_bits[1];
		mul_23 <= mul_bits[2] + mul_bits[3];
		mul_out <= mul_01+mul_23;
	end
end





//size级流水线




endmodule