题解 | 占空比50%的奇数分频

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//计数器  4个时钟的低电平，3个时钟的高电平
reg [2:0] cnt;
always@(posedge clk_in or negedge rst) begin
    if(!rst)begin
        cnt <= 'd0;
    end
    else if(cnt == 'd6)begin
        cnt <= 'd0;
    end
    else begin
        cnt <= cnt + 1;
    end

end
//上升沿
reg clk_r;
always@(posedge clk_in or negedge rst) begin
    if(!rst)begin
        clk_r <= 1'b0;
    end
    else if(cnt=='d3)begin		//4 5 6 三个时钟的高电平
        clk_r <= 1'b1;
    end
    else if(cnt =='d6)begin		// 0 1 2 3 四个时钟的低电平
        clk_r <= 1'b0;
    end
end
//下降沿
reg clk_f;
always@(negedge clk_in or negedge rst) begin
    if(!rst)begin
        clk_f <= 1'b0;
    end
    else if(cnt=='d3)begin
        clk_f <= 1'b1;
    end
    else if(cnt =='d6)begin
        clk_f <= 1'b0;
    end
end
//或输出
assign clk_out7 = clk_f | clk_r ;
endmodule