题解 | 交通灯

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output reg [7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );

    parameter IDLE  = 3'b000;
    parameter GRE   = 3'b001;
    parameter YEL   = 3'b010;
    parameter RED   = 3'b100;
    parameter RED_1 = 3'b101;		//复位两个时钟红灯
    parameter RED_2 = 3'b111;
    reg [2:0] state;
    reg [2:0] nextstate;

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            state <= IDLE;
        end
        else begin
            state <= nextstate;
        end
    end
	// 红灯->黄灯->绿灯  
    always@(*)begin
        case(state)
        IDLE:begin
            nextstate = RED_1;
        end
        RED_1:begin
            nextstate = RED_2;
        end
        RED_2:begin
            nextstate = RED;
        end
        GRE :begin
            if(clock == 'd1)begin
                nextstate = RED;
            end
            else begin
                nextstate = GRE;
            end
        end
        YEL :begin
            if(clock == 'd1)begin
                nextstate = GRE;
            end
            else begin
                nextstate = YEL;
            end
        end
        RED :begin
            if(clock == 'd1)begin
                nextstate = YEL;
            end
            else begin
                nextstate = RED;
            end
        end
        default:nextstate = IDLE;
        endcase
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) begin
            clock <= 'd10;
        end
        else begin
            case(state)
            RED_2:begin
                clock <= 'd10;
            end
            GRE :begin
                if(pass_request && (clock > 'd10))begin
                    clock <= 'd10;
                end
                else if(clock == 'd1) begin
                    clock <= 'd10;
                end
                else begin
                    clock <= clock - 1'b1;
                end
            end
            YEL :begin
                if(clock == 'd1) begin
                    clock <= 'd60;
                end
                else begin
                    clock <= clock - 1'b1;
                end
            end
            RED :begin
                if(clock == 'd1) begin
                    clock <= 'd5;
                end
                else begin
                    clock <= clock - 1'b1;
                end
            end
            default:clock <= clock - 1'b1;
            endcase
        end
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) begin
            red <= 1'b0;
        end
        else if(nextstate == RED) begin
            red <= 1'b1;
        end
        else begin
            red <= 1'b0;
        end
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) begin
            yellow <= 1'b0;
        end
        else if(nextstate == YEL) begin
            yellow <= 1'b1;
        end
        else begin
            yellow <= 1'b0;
        end
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) begin
            green <= 1'b0;
        end
        else if(nextstate == GRE) begin
            green <= 1'b1;
        end
        else begin
            green <= 1'b0;
        end
    end
	
endmodule