题解 | 输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [3:0] data_tmp;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		data_tmp <= 4'b0;
	end
	else
	if(data_valid)
	begin
		data_tmp <= {data_tmp[2:0] , data};
	end
	else
	begin
		data_tmp <= data_tmp;
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		match <= 0;
	end
	else
	if(data_tmp[2:0] == 3'b011 && data==1'b0 && data_valid)//这块时序只有是这样才对
		begin
			match <= 1;  
		end
		else
		begin
			match <= 0;
		end
end

  
endmodule