题解 | 自动贩售机2（mealy三段）

和上一题一样，对输入寄存用mealy三段，注意输出逻辑要排除{d2,d1}==2'b00的情况

输入控制有sel和d2,d1，寄存为sel_reg和inp_reg

`timescale 1ns / 1ns

module seller2 (
    input wire clk,
    input wire rst,
    input wire d1,
    input wire d2,
    input wire sel,

    output reg out1,
    output reg out2,
    output reg out3
);
    //*************code***********//
    reg [1:0] inp_reg;
    reg sel_reg;
    // assign inp_reg={d2,d1};
    localparam [2:0] S0 = 3'b000, S5 = 3'b001, S10 = 3'b010, S15 = 3'b011, S20 = 3'b100;
    reg [2:0] cs, ns;
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            inp_reg <= 0;
            sel_reg <= 0;
        end else begin
            inp_reg <= {d2, d1};
            sel_reg <= sel;
        end
    end
    always @(posedge clk or negedge rst) begin
        if (!rst) cs <= S0;
        else cs <= ns;
    end
    always @(*) begin
        case (cs)
            S0:
            case (inp_reg)
                2'b01:   ns = S5;
                2'b10:   ns = S10;
                default: ns = cs;
            endcase
            S5:
            case (inp_reg)
                2'b01:   ns = S10;
                2'b10:   ns = sel_reg ? S10 : S0;
                default: ns = cs;
            endcase
            S10:
            case (inp_reg)
                2'b01:   ns = sel_reg ? S15 : S0;
                2'b10:   ns = sel_reg ? S20 : S0;
                default: ns = cs;
            endcase
            S15:
            case (inp_reg)
                2'b01:   ns = S20;
                2'b10:   ns = S0;
                default: ns = cs;
            endcase
            S20:
            case (inp_reg)
                2'b01:   ns = S0;
                2'b10:   ns = S0;
                default: ns = cs;
            endcase
            default: ns = S0;
        endcase
    end
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            out1 <= 0;
            out2 <= 0;
            out3 <= 0;
        end else begin
            case (sel_reg)
                0: begin
                    out1 <= (cs == S5 && inp_reg == 2'b10) | (cs == S10 && inp_reg == 2'b10) | (cs == S10 && inp_reg == 2'b01);
                    out2 <= 0;
                    out3 <= (cs == S10 && inp_reg == 2'b10);
                end
                1: begin
                    out1 <= 0;
                    out2 <= (cs == S15 && inp_reg == 2'b10) | (cs == S20 && inp_reg == 2'b10) | (cs == S20 && inp_reg == 2'b01);
                    out3 <= (cs == S20 && inp_reg == 2'b10);
                end
            endcase
        end
    end


    //*************code***********//
endmodule