题解 | 非整数倍数据位宽转换8to12

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);    reg [2:0] cnt;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cnt <= 0;
        end else if (valid_in) begin
            cnt <= (cnt == 'd2) ? 0 : cnt + 1;
        end
    end
    reg [7:0] data_lock;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            data_lock <= 0;
        end else if (valid_in) begin
            data_lock <= data_in;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            valid_out <= 0;
        end else if (valid_in && ((cnt == 'd1) || (cnt == 'd2))) begin
            valid_out <= 1;
        end else begin
            valid_out <= 0;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            data_out <= 0;
        end else if (valid_in) begin
            case (cnt)
                2'd1: data_out <= {data_lock, data_in[7:4]};
                2'd2: data_out <= {data_lock[3:0], data_in};
                default: data_out <= data_out;
            endcase
        end
    end
endmodule

之前写过一个错误版本的valid_out逻辑

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            valid_out <= 0;
        end else if (valid_in) begin
            valid_out <= (cnt == 'd1) || (cnt == 'd2);
        end 
    end

显然我忽略了valid_out的脉冲行为，会生成保持态，因此还需要一个else来矫正为脉冲。