题解 | 根据状态转移写状态机-三段式

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

localparam S0 = 2'b00;
localparam S1 = 2'b01;
localparam S2 = 2'b10;
localparam S3 = 2'b11;

reg [1:0] cur_state;
reg [1:0] next_state;
always @(posedge clk or negedge rst) begin
	if (!rst) begin
		cur_state <= 2'b00;
	end
	else begin
		cur_state <= next_state;
	end
end

always @(*) begin
	case (cur_state) 
		S0: begin
			next_state = (data == 1'b1) ? S1 : S0;
		end
		S1: begin
			next_state = (data == 1'b1) ? S2 : S1;
		end
		S2: begin
			next_state = (data == 1'b1) ? S3 : S2;
		end
		S3: begin
			next_state = (data == 1'b1) ? S0 : S3;
		end
	endcase
end

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		flag <= 1'b0;
	end 
	else if (cur_state == S3 && next_state == S0) begin
		flag <= 1'b1;
	end 
	else begin
		flag <= 1'b0;
	end
end
//*************code***********//
endmodule