题解 | 移位运算与乘法

`timescale 1ns/1ns
module multi_sel(
    input [7:0] d,
    input clk,
    input rst,  
    output reg input_grant,
    output reg [10:0] out
);

reg [1:0] grant_cnt;
reg [10:0] din;

// grant_cnt计数
always @(posedge clk or negedge rst) begin
    if (!rst) begin
        grant_cnt <= 0;
    end else if (grant_cnt == 2'd3) begin
        grant_cnt <= 0;
    end else begin
        grant_cnt <= grant_cnt + 1'b1;
    end
end

// input_grant 控制
always @(posedge clk or negedge rst) begin
    if (!rst) begin
        input_grant <= 1'b0;
    end else if (grant_cnt == 2'd0) begin
        input_grant <= 1'b1;
    end else begin
        input_grant <= 1'b0;
    end
end

// 数据处理逻辑
always @(posedge clk or negedge rst) begin
    if (!rst) begin
        out <= 11'd0;
        din <= 11'd0;
    end else begin
        case (grant_cnt)

            2'd0: begin
                din <= d;
                out <= d;
            end
            2'd1: begin
                out <= (din << 2) - din;  // din * 3
            end
            2'd2: begin
                out <= (din << 3) - din;  // din * 7
            end
            2'd3: begin
                out <= (din << 3);        // din * 8
            end
        endcase
    end
end

endmodule