题解 | 占空比50%的奇数分频

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
//从图上可以看出：clk下降沿clk_out变1，clk上升沿clk_out变0；
reg clk_pos;//clk上升沿翻转
reg clk_neg;//clk下降沿翻转
reg [2:0] cnt;
always@(posedge clk_in or negedge rst)
if(!rst)
  cnt <= 0;
else
  cnt <= (cnt==3'd6) ? 0 : (cnt+1);

always@(posedge clk_in or negedge rst)
if(!rst)
  clk_pos <= 0;
else
  clk_pos <= (cnt==3||cnt==6)?(~clk_pos):clk_pos;

always@(negedge clk_in or negedge rst)
if(!rst)
  clk_neg <= 0;
else
  clk_neg <= (cnt==3||cnt==6)?(~clk_neg):clk_neg;

assign clk_out7 = clk_pos|clk_neg;



//*************code***********//
endmodule