题解 | 根据RTL图编写Verilog程序

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

reg q1;

always @(posedge clk or negedge rst_n) begin
       if (~rst_n) begin
			q1 <= 1'b0;
	   end else begin
			q1 <= data_in;
	   end
end

always @(posedge clk or negedge rst_n) begin
       if (~rst_n) begin
			data_out <= 1'b0;
	   end else begin
			data_out <= data_in & ~q1;
	   end
end
endmodule