题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);
	
	reg [2:0]cnt ;
	reg valid_in_r = 'd0;
	reg [3:0]dout_r = 'd0;
	assign dout = dout_r[3];
	assign valid_in = valid_in_r;
//*************code***********//
	always@(posedge clk or negedge rst)begin
		if(!rst)
			cnt <= 0;
		else if(cnt == 3)
			cnt <= 0;
		else
			cnt <= cnt + 1;
	end 

	always@(posedge clk or negedge rst)begin
		if(!rst)
			valid_in_r <= 0;
		else if(cnt == 3)
			valid_in_r <= 1;
		else
			valid_in_r <= 0;
	end 
	always@(posedge clk or negedge rst)begin
		if(!rst)
			dout_r <= 0;
		else if(cnt == 3)
			dout_r <= d;
		else
			dout_r <= {dout_r[2:0],dout_r[3]} ;
	end 
//*************code***********//

endmodule