题解 | #四选一多路器#

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
reg [1:0] mux_out_r;
always@(*)begin
    case(sel)
        2'b00:mux_out_r = d3;
        2'b01:mux_out_r = d2;
        2'b10:mux_out_r = d1;
        2'b11:mux_out_r = d0;
        default:mux_out_r = 2'd0;
    endcase

end
assign mux_out = mux_out_r;
//*************code***********//
endmodule