题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg [1:0] a1a0;

always @(posedge clk or negedge rst_n) begin
	if(rst_n == 1'b0) begin
		a1a0 <= 2'b00;
	end
	else begin
		a1a0 <= {a1a0[0],a};
	end	
end

always @(*) begin
	if(rst_n == 1'b0) begin
		rise <= 1'b0;
		down <= 1'b0;
	end
	else if(a1a0 == 2'b01) begin
		rise <= 1'b1;
	end
	else if(a1a0 == 2'b10) begin
		down <= 1'b1;
	end
	else begin
		rise <= 1'b0;
		down <= 1'b0;
	end	
end
	
endmodule