题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input wire [7:0]d ,
input wire clk,
input wire rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [1:0] cnt;
reg [10:0] din;

always@(posedge clk or negedge rst)
    if(!rst)
        cnt<=2'd0;
    else
        cnt<=cnt+1'b1;

always@(posedge clk or negedge rst)
    if(!rst)
        din<=8'd0;
    else if(cnt==2'd0)
        din<=d;
    else
        din<=din;

always@(posedge clk or negedge rst)
    if(!rst)
        input_grant<=1'b0;
    else if(cnt==2'd0)
        input_grant<=1'b1;
    else
        input_grant<=1'b0;

always@(posedge clk or negedge rst)
    if(!rst)
        out<=11'd0;
    else
        case(cnt)
            2'd0 : out<=d;
            2'd1 : out<=din+(din<<1);
            2'd2 : out<=din+(din<<1)+(din<<2);
            2'd3 : out<=din<<3;
        endcase

//*************code***********//
endmodule