题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

reg [2:0] cnt_state;
reg [3:0] seq_r;

always@(posedge clk or negedge rst)begin
	if(!rst)begin
		cnt_state <= 0;
		flag <= 0;
		seq_r <= 0;
	end
	else begin
		case(cnt_state)
			3'd0 : begin 
				cnt_state <= (data) ? cnt_state + 1'b1 : cnt_state;
				flag <= 0;
				seq_r[0] <= (data) ? 1'b1 : 1'b0;
			end
			3'd1 : begin
				cnt_state <= cnt_state + 1'b1;
				flag <= 0;
				seq_r[1] <= (!data) ? 1'b1 : 1'b0;
			end
			3'd2 : begin
				cnt_state <= cnt_state + 1'b1;
				flag <= 0;
				seq_r[2] <= (data) ? 1'b1 : 1'b0;
			end
			3'd3 : begin
				cnt_state <= cnt_state + 1'b1;
				flag <= 0;
				seq_r[3] <= (data) ? 1'b1 : 1'b0;
			end
			3'd4 : begin
				cnt_state <= 3'd0;
				flag <= (&{seq_r,data}) ? 1'b1 : 1'b0;
				seq_r <= 0;
			end
			default : begin
				seq_r <= 0;
				cnt_state <= 3'd0;
				flag <= 0;
			end
		endcase
	end
end



//*************code***********//
endmodule