题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [9:0] cs;
reg [9:0] ns;

parameter IDLE = 10'b00_0000_0001,
            S0 = 10'b00_0000_0010,
            S1 = 10'b00_0000_0100,
            S2 = 10'b00_0000_1000,
            S3 = 10'b00_0001_0000,
            S4 = 10'b00_0010_0000,
            S5 = 10'b00_0100_0000,                                    
            S6 = 10'b00_1000_0000,
            S7 = 10'b01_0000_0000,
            S8 = 10'b10_0000_0000;

//1st
always @ (posedge clk or negedge rst_n)
begin
	if (~rst_n)
	   cs <= IDLE;
    else
	   cs <= ns;
end	   

//2nd
always @ (*)
begin
	case(cs)
	    IDLE : ns = (a == 1'b0)? S0 :IDLE;
		  S0 : ns = (a == 1'b1)? S1 :IDLE;
		  S1 : ns = (a == 1'b1)? S2 :IDLE;
		  S2 : ns = S3;
		  S3 : ns = S4;
		  S4 : ns = S5;
		  S5 : ns = (a == 1'b1)? S6 :S0;	
		  S6 : ns = (a == 1'b1)? S7 :S0;		  	  
		  S7 : ns = (a == 1'b0)? S8 :IDLE;
		  S8 : ns = (a == 1'b1)? IDLE :S0;
	endcase
end

//3rd  
reg match_tmp;  //根据波形，序列a符合要求之后还要打一拍再输出match 
always @ (posedge clk or negedge rst_n)
begin
	if (~rst_n) begin
	   match_tmp <= 1'b0;
	   match <= 1'b0;
	end   
    else begin
	   match_tmp <= (ns == S8);   //不要用错成cs
	   match <= match_tmp;
	end   
end	   





endmodule