题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//

reg [2:0] cnt_p, cnt_n;
always@(posedge clk_in, negedge rst) begin
    if(!rst) begin
        cnt_p <= 3'd0;
    end
    else begin
        if(cnt_p == 3'd6) cnt_p <= 3'd0;
        else cnt_p <= cnt_p + 3'd1;
    end
end
always@(negedge clk_in, negedge rst) begin
    if(!rst) begin
        cnt_n <= 3'd0;
    end
    else begin
        if(cnt_n == 3'd6) cnt_n <= 3'd0;
        else cnt_n <= cnt_n + 3'd1;
    end
end

wire clk_p, clk_n;
assign clk_p = rst?(cnt_p > 3'd3):1'b0;
assign clk_n = rst?(cnt_n > 3'd3):1'b0;

assign clk_out7 = clk_p | clk_n;
//*************code***********//
endmodule