题解 | #时钟切换#

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output wire clk_out
);
//*************code***********//
reg sel_clk0;
reg sel_clk1;
wire sel_clk0_n;
wire sel_clk1_n;
wire sel_clk0_in;
wire sel_clk1_in;
wire sel_clk1_out;
wire sel_clk0_out;
//*************code***********//
assign sel_clk1_n = ~sel_clk1            ;
assign sel_clk1_in = sel & sel_clk0_n   ;//告诉另一个时钟沿已经关闭

assign sel_clk0_n = ~sel_clk0            ;
assign sel_clk0_in = (~sel) & sel_clk1_n;//告诉另一个时钟沿已经关闭
assign sel_clk0_out = clk0 & sel_clk0    ;//搬移到低电平跳变的sel 信号
assign sel_clk1_out = clk1 & sel_clk1    ;//搬移到低电平跳变的sel 信号
//下降沿触发器
always@(negedge clk1 or negedge rst)
begin
	if(!rst)
		sel_clk1<=0;
	else
		sel_clk1<=sel_clk1_in;
end

always@(negedge clk0 or negedge rst)
begin
	if(!rst)
		sel_clk0<=0;
	else
		sel_clk0<=sel_clk0_in;
end

assign clk_out = sel_clk1_out|sel_clk0_out;
endmodule
//避免毛刺：1.当一路时钟使能的时候，必须知道另一路时钟已经关闭（避免竞争冒险，触发器反向输出反馈） 2.sel切换信号必须在两个时钟低电平的时候跳变，防止产生尖峰（下降沿打拍）