题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [3:0] data_reg;

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_reg <= 4'b0;
	end
	else begin
		if(data_valid) begin
			data_reg <= {data_reg[2:0], data};
		end
		else begin
			data_reg <= data_reg;
		end
	end
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        match <= 1'b0;
    end
    else begin
        if (data_valid && ({data_reg[2:0], data} == 4'b0110)) begin
            match <= 1'b1;
        end
        else begin
            match <= 1'b0;
        end
    end
end
/* 这种情况match可能会持续多个周期
always @(*) begin
    if (data_reg == 4'b0110) begin
        match <= 1'b1;
    end
    else begin
        match <= 1'b0;
    end
end
*/
endmodule