题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
reg [3:0] romreg[7:0];
integer i;
always @ (posedge clk or negedge rst_n)
begin
    if( ~rst_n ) begin
        romreg[0] <= 4'd0;
        romreg[1] <= 4'd2;
        romreg[2] <= 4'd4;
        romreg[3] <= 4'd6;
        romreg[4] <= 4'd8;
        romreg[5] <= 4'd10;
        romreg[6] <= 4'd12;
        romreg[7] <= 4'd14;
    end 
    else begin
        // romreg[0] <= romreg[0];
        // ...
        // romreg[7] <= romreg[7];
        for(i = 0; i < 8; i = i+1) begin : rom_i
            romreg[i] <= romreg[i];
        end 
    end 
end

assign data = romreg[addr];
endmodule